The present invention relates to a semiconductor device with a MOS transistor mounted thereon and a method of manufacturing the same. More particularly, it relates to a method of implementing a semiconductor device of super-high integration which is operable at higher speed and exhibits stabilized device characteristics.
As higher integration and higher-speed operation have been required of semiconductor devices in recent years, transistors and wires mounted thereon and connection holes formed therein have been increasingly miniaturized. For instance, a MOS transistor having a reduced gate length of 0.4 .mu.m has been implemented on a manufacturing level.
To achieve further miniaturization, it is required from the viewpoint of the manufacturing apparatus to use exposing light at a shorter wavelength and an improved exposure method in the photolithographic process for patterning a gate electrode. In principle, a light source which generates light at a shorter wavelength is more suitable for exposure. At present, exposing light at the shortest wavelength in practical use is an i line (at a wavelength of 365 nm) radiated from a mercury lamp. On the other hand, a KrF eximer laser beam has reached a point where it is substantially practical.
To provide an improved exposure method, new technology has been proposed and developed which increases resolving power by modifying optical systems and thereby forms a micropattern smaller in size than the wavelength of exposing light. For example, the modified illumination method is based on the principle of optical microscopy using the interference of two luminous fluxes, which involves the use of obliquely incident light for exposure in order to increase resolving power. On the other hand, the phase shift method uses a phase shifter provided on a mask in order to cause an interference between light that has passed through the phase shifter and hence in inverted phase and light that has not passed through the phase shifter, thereby increasing resolving power for separating openings in the mask. With these methods, the depth of focus is increased and a clear image can be formed constantly on a photoresist film even when the thickness of the photoresist film slightly varies from one place to another. In accordance with the methods, therefore, it is possible in principle to form a micropattern with about 0.3 .mu.m minimum features by using, e.g., the i line.
Miniaturization has also been pursued in the structure of a MOS transistor to implement a microstructure suitable for practical use. Referring now to the drawings, a description will be given to a conventional semiconductor device and a manufacturing method thereof for achieving higher integration and high-speed operation.
FIG. 14 is a cross sectional view showing the structure of a conventional single MOS transistor. Below, the structure shown in FIG. 14 and the manufacturing method for implementing the structure will be roughly described.
Initially, an isolation 17 composed of a silicon dioxide film with a thickness of about 400 nm is formed by a LOCOS method on a semiconductor substrate 10. Then, a silicon dioxide film with a thickness of 10 nm and a polysilicon film with a thickness of 300 nm are successively deposited in this order. The polysilicon film and silicon dioxide film are selectively removed by subsequent photolithographic and etching processes, thereby forming a gate insulating film 15 and a gate electrode 50. At this stage, impurity ions at a low concentration are implanted using the gate electrode 50 as a mask so as to form LDD regions 21a. Thereafter, a silicon dioxide film with a thickness of about 150 nm is deposited by CVD over the entire surface, which is then etched back to form sidewalls 20. Subsequently, impurity ions at a high concentration are implanted into the semiconductor substrate 10 by using the gate electrode 50 and sidewalls 20 as a mask, thereby forming source/drain regions 21b. Next, an interlayer insulating film 32 is deposited and subjected to photolithographic and etching processes for opening contact holes therein, followed by the formation of metal buried layers 33 and the formation of aluminum interconnections 34 to be connected to the metal layers.
FIG. 15 is a plan view showing an example of the layout of a conventional semiconductor device on which a plurality of MOS transistors formed by the above manufacturing method are mounted.
In the example shown in the drawing, three transistors TR1 to TR3 are formed in a common first active region Rea1, while one transistor TR4 is formed isolated in a second active region Rea2. The semiconductor device formed by the conventional manufacturing method is so constituted that the source/drain regions 21b of the MOS transistors are connected to the corresponding upper metal interconnections 34 via the buried layers 33 in the contact holes.
Since the above structure suppresses a so-called narrow channel effect, the gate length can be reduced advantageously.
However, although the conventional semiconductor device of the above structure enables reductions in size of individual components, the following two problems inhibit further miniaturization, i.e., higher integration of the whole semiconductor device which has taken full advantage of the improved resolving power achieved in the manufacturing apparatus described above.
The first problem is variations in size in the photolithographic and etching processes. More specifically, as features to be defined by processing are increasingly miniaturized in the photolithographic process, influences of a difference in level in the underlay, such as halation and standing-wave effect, and the dependence of the sizes of such components as the gate electrode on the pattern due to the proximity effect become more conspicuous. In the etching process also, it becomes difficult to suppress an effect which varies the etching rate depending on a variation in the surface area of a portion being etched, i.e., the microloading effect. As a result, the respective gate electrodes 50 of the four MOS transistors TR1 to TR4 shown in FIG. 15 actually have different sizes L1 to L4, though they are originally designed to have the same size. Below, a description will be given to the variations in size.
FIG. 16 shows, for comparison, a distribution of the finished sizes of the gate length in an isolated pattern and a distribution of the finished sizes of the gate length in a line-and-space pattern (with three lines) in the case where gate electrodes are patterned by lithographic method in a pattern in which the gate length is 0.4 .mu.m. As shown in the drawing, the finished sizes of the gate length in the isolated pattern are shifted in such a direction that the central value thereof becomes larger than the central value of the finished sizes of the gate length in the line-and-space pattern by about 0.08 .mu.m. Even in a common dense pattern (line-and-space pattern), the gate electrode 50 of the middle one of the three transistors TR1 to TR3 tends to have a length shorter than those of the gate electrodes 50 on both sides, since it is most susceptible to the influences including the proximity effect.
The sizes L1 to L4 are thus varied, the correlation of which is represented by L4&gt;L3=L1&gt;L2. Such variations in size are not reduced at the same ratio as the gate length is reduced. If miniaturization is pursued in defiance of such size variations, a relative error between the sizes of the individual components is increased, which may seriously affect the characteristics of the transistors.
The second problem is a displacement of masks in the photolithographic process. In contrast to remarkable progresses achieved in microprocessing technology, technology of mask alignment has not improved greatly in terms of accuracy. To prevent defective characteristics or a reduced yield resulting from a short circuit between the source/drain regions and the gate electrode or substrate, it is required to lay out the contact holes, the gate electrode, and an isolation region at least at minimum specified intervals. In other words, it is necessary to previously provide the designed size with a margin for mask alignment.
Accordingly, even with an improved exposure method and an improved structure of the source/drain regions, reductions in size of the gate electrode, connections holes, and the like, which are commensurate with the remarkable progresses in microprocessing technology, cannot be attained because of the above problems which present obstacles to miniaturization. At the present stage, the above two problems have become factors which inhibit higher integration and higher-speed operation of the whole semiconductor device and their influences become more serious as miniaturization increases.